The invention relates generally to the field of semiconductor devices, particularly to gate arrays and, more particularly, to user-programmable or field programmable gate arrays (FPGAs).
A gate array, a type of integrated circuit device, is largely a matrix of circuit elements, such as transistors, logic gates and their associated input and output circuits. These circuit elements are overlaid with one or more interconnection layers, which connect the transistors, logic gates and the input and output circuits in a pattern to perform a user-specified function.
Conventional, or mask-programmable, gate arrays (MPGAs) are created by building the integrated circuit up to the interconnect level. After the interconnect pattern is specified by the user, the wiring channels are created by depositing, masking, and etching the metal interconnection layers and contact layers to make the connections for the desired logic cells and the input and output circuits to perform the user-specified function. The creation of the wiring channels, i.e., the programming of the device, is done by the manufacturer of the MPGA.
However, disadvantages of MPGAs include the long period between the design and specification of the desired interconnect pattern and the receipt of the completed device, plus the large nonrecurring engineering cost involved in each design and specification iteration. These disadvantages make MPGAs uneconomical in small production volumes.
Another type of gate array, the field programmable gate array (FPGA), address some of these problems. The FPGA is completely formed with a global set of vertical and horizontal wiring channels which are built into the device. However, these channels are electrically isolated from the logic cells, the input and output circuits, and each other, by electrically programmable interconnect elements. One such element is an antifuse. The user programs these antifuses to define the specified interconnection pattern for the user's application, very rapidly and at the user's own facility. The elapsed time from design specification to receipt of completed parts is measured in minutes instead of months. The nonrecurring engineering cost is also avoided.
However, FPGAs heretofore have had certain disadvantages in performance and use with respect to MPGAs. In a MPGA the programmable transistors are arranged in either small units of transistors, typically 4 or 6 transistors, which are electrically tied together into a functioning cell, or into an array of series-connected transistors (sometimes called continuous-series transistors, or CSTs) in which the source/drain of one MOS transistor merges into the source/drain of a neighboring MOS transistor. In both cases the metal interconnection lines of the MPGA connect various nodes of the units or the series-connected transistors to configure the units or transistors into various logic gate cells or larger logic blocks, as desired by the specific application.
Instead of these small units and individual transistors, present day FPGAs use arrays of configurable logic blocks which have many transistors. This type of organization is inefficient in implementing small logic gates and inverters, of which a large percentage exist in MPGA designs. The large logic blocks of present day FPGAs provide poor gate utilization and operate at speeds too slow for designs using MPGA logic methodology.
Furthermore, these FPGAs, once programmed, do not behave like an identically-programmed MPGA. Because of the large numbers of users already familiar with the architecture and usage of MPGAs, it is desirable that the FPGA match a MPGA in gate density and performance.
The present invention offers a FPGA which is not only compatible with MPGAs, but also has performance levels comparable to that of a MPGA. In doing so, the present invention solves or substantially mitigates many of the problems of present day FPGAs.